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DG428/429
Vishay Siliconix
Single 8-Ch/Differential 4-Ch Latchable Analog Multiplexers
FEATURES
D Low rDS(on): 55 W D Low Charge Injection: 1 pC D On-Board TTL Compatible Address Latches D High Speed--tTRANS: 160 ns D Break-Before-Make D Low Power Consumption: 0.3 mW
BENEFITS
D D D D D D Improved System Accuracy Microprocessor Bus Compatible Easily Interfaced Reduced Crosstalk High Throughput Improved Reliability
APPLICATIONS
D D D D D Data Acquisition Systems Automatic Test Equipment Avionics and Military Systems Communication Systems Microprocessor-Controlled Analog Systems D Medical Instrumentation
DESCRIPTION
The DG428/DG429 analog multiplexers have on-chip address and control latches to simplify design in microprocessor based applications. Break-before-make switching action protects against momentary crosstalk of adjacent input signals. The DG428 selects one of eight single-ended inputs to a common output, while the DG429 selects one of four differential inputs to a common differential output. An on channel conducts current equally well in both directions. In the off state each channel blocks voltages up to the power supply rails. An enable (EN) function allows the user to reset the multiplexer/demultiplexer to all switches off for stacking several devices. All control inputs, address (Ax) and enable (EN) are TTL compatible over the full specified operating temperature range. The silicon-gate CMOS process enables operation over a wide range of supply voltages. The absolute maximum voltage rating is extended to 44 V. Additionally, single supply operation is also allowed and an epitaxial layer prevents latchup. On-board TTL-compatible address latches simplify the digital interface design and reduce board space in bus-controlled systems such as data acquisition systems, process controls, avionics, and ATE.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG428
Dual-In-Line A0
DG428
PLCC WR 18 17 RS A1 A2 GND V+ S5 S6 S7 S8 9 S4 10 11 12 13 S8 NC S7 D EN V- S1 S2 S3 4 5 6 7 8 Latches Decoders/Drivers 18 17 16 15 14 A2 GND V+ S5 S6 A1 NC 1 RS
WR A0 EN V- S1 S2 S3 S4 D
1 2 3 4 5 6 7 8 9 Latches Decoders/Drivers
3
2
20 19
16 15 14 13 12 11 10
Top View Top View
Document Number: 70063 S-52433--Rev. J, 06-Sep-99
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DG428/429
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG429
Dual-In-Line and SOIC A0
DG429
PLCC WR 18 17 RS A1 GND V+ S1b S2b S3b S4b Db 9 S4a 10 11 12 13 S4b Da NC Db EN V- S1a S2a S3a 4 5 6 7 8 Latches Decoders/Drivers 18 17 16 15 14 GND VDD S1b S2b S3b A1 NC 1 RS
WR A0 EN V- S1a S2a S3a S4a Da
1 2 3 4 5 6 7 8 9 Latches Decoders/Drivers
3
2
20 19
16 15 14 13 12 11 10
Top View Top View
TRUTH TABLE
A2 A1 A0 EN WR RS
DG428
On Switch A1 A0
TRUTH TABLE
EN WR RS
DG429
On Switch
8-Channel Single-Ended Multiplexer Latching
X X 1 Maintains previous switch condition X X
Differential 4-Channel Multiplexer
Latching
X X
X
1
Maintains previous switch condition
Reset
X X X X X 0 None (latches cleared)
Reset
X X X X 0 None (latches cleared)
Transparent Operation
X 0 0 0 0 1 1 1 1 X 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 None 1 2 3 4 5 6 7 8
Transparent Operation
X 0 0 1 1 X 0 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 None 1 2 3 4
Logic "0" = VAL v 0.8 V Logic "1" = VAH w 2.4 V X = Don't Care
ORDERING INFORMATION Temp Range
-40 to 85_C
DG428 Part Number
DG428DJ DG428DN
ORDERING INFORMATION Temp Range
-40 to 85 C 40 85_C
DG429 Part Number
DG429DJ DG429DN DG429DW
Package
18-Pin Plastic DIP 20-Pin PLCC
Package
18-Pin Plastic DIP 20-Pin PLCC 18-Pin Widebody SOIC
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Document Number: 70063 S-52433--Rev. J, 06-Sep-99
DG428/429
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltage Referenced to V- V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Digital Inputsa, VS, VD . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2 V to (V+) +2 V or 30 mA, whichever occurs first Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Storage Temperature (AK Suffix) . . . . . . . . . . . . . . . . . . -65 to 150_C (DJ, DN Suffix) . . . . . . . . . . . . . . -65 to 125_C Power Dissipation (Package)b 18-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW 18-Pin CerDIPd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW 20-Pin PLCCf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW 28-Pin Widebody SOICf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW Notes: a. Signals on SX, DX or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads soldered or welded to PC board. c. Derate 6.3 mW/_C above 75_C. d. Derate 12 mW/_C above 75_C. e. Derate 10 mW/_C above 75_C. f. Derate 6 mW/_C above 75_C.
SPECIFICATIONSa
Test Conditions Unless Otherwise Specified Parameter Analog Switch
Analog Signal Rangee Drain-Source On-Resistance Greatest Change in rDS(on) Between Channelsg Source Off Leakage Current Drain Off Leakage Current Lk C t VANALOG rDS(on) DrDS(on) IS(off) VD = "10 V, VAL = 0.8 V IS = -1 mA, VAH = 2.4 V -10 V < VS < 10 V IS = -1 mA VS = "10 V, VD = #10 V VEN = 0 V VD = "10 V VS = #10 V VEN = 0 V VS = VD = "10 V VEN = 2.4 V VAL = 0 8 V 0.8 VAH = 2.4 V DG428 DG429 DG428 DG429 Full Room Full Room Room Full Room Full Room Full Room Full Room Full 55 5 "0.03 "0.07 "0.05 "0.07 "0.05 -0.5 -50 -1 -100 -1 -50 -1 -100 -1 -50 0.5 50 1 100 1 50 1 100 1 50 -0.5 -50 -1 -100 -1 -50 -1 -100 -1 -50 0.5 50 1 100 1 50 1 100 1 50 nA A -15 15 100 125 -15 15 100 125 V W %
A Suffix
-55 to 125_C
D Suffix
-40 to 85_C
Symbol
V+ = 15 V, V- = -15 V, WR = 0, RS = 2.4 V, VIN = 2.4 V, 0.8 Vf
Tempb
Typc
Mind
Maxd
Mind
Maxd
Unit
ID(off)
Drain On Leakage Current Lk C t
ID(on)
Digital Control
Logic Input Current g p Input V lt I t Voltage High Hi h Logic Input Current Input Voltage Low Logic Input Capacitance IAH IAL Cin VA = 2.4 V VA = 15 V VEN = 0 V, 2.4 V, VA = 0 V RS = 0 V, WR = 0 V f = 1 MHz Full Full Full Room 0.01 0.01 -0.01 8 -1 1 1 -1 pF 1 1 mA A
Dynamic Characteristics
Transition Time Break-Before-Make Interval Enable and Write Turn-On Time Enable and Reset Turn-Off Time Charge Injection Off Isolation Source Off Capacitance Drain Off Capacitance tTRANS tOPEN tON(EN,WR) tOFF(EN,RS) Q OIRR CS(off) CD(off) VD = 0 V, VEN = 0 V V, f = 1 MHz MH Drain On Capacitance CD(on) See Figure 5 See Figure 4 See Figures 6 and 7 See Figures 6 and 8 VGEN = 0 V, RGEN = 0 W CL = 1 nF, See Figure 9 VEN = 0 V, RL = 300 W, CL = 15 pF VS = 7 VRMS, f = 100 kHz VS = 0 V, VEN = 0 V, f = 1 MHz DG428 DG429 DG428 DG429 Room Full Full Room Full Room Full Room Room Room Room Room Room Room 150 30 90 55 10 150 225 150 300 250 300 10 150 225 150 300 pC dB ns 250 300
1 -75 11 40 20 54 34
pF F
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SPECIFICATIONSa
Test Conditions Unless Otherwise Specified Parameter Symbol
V+ = 15 V, V- = -15 V, WR = 0, RS = 2.4 V, VIN = 2.4 V, 0.8 Vf
A Suffix
-55 to 125_C
D Suffix
-40 to 85_C
Tempb
Typc
Mind
Maxd
Mind
Maxd
Unit
Minimum Input Timing Requirements
Write Pulse Width AX, EN Data Set Up time AX, EN Data Hold Time Reset Pulse Width tW tS tH tRS VS = 5 V, See Figure 3 See Figure 2 S Fi Full Full Full Full 100 100 10 100 100 100 10 100 ns
Power Supplies
Positive Supply Current Negative Supply Current I+ I- VEN = 0 V, VA = 0, RS = 5 V V 0 Room Room 20 -0.001 -5 100 -5 100 mA
SPECIFICATIONSa FOR SINGLE SUPPLY
Test Conditions Unless Otherwise Specified Parameter Analog Switch
Analog Signal Rangee Drain-Source On-Resistance rDS(on) Matchg Source Off Leakage Current Drain Off Leakage Current VANALOG rDS(on) DrDS(on) IS(off) VD = +10 V, VAL = 0.8 V IS = -500 mA, VAH = 2.4 V 0 V < VS < 10 V IS = -1 mA VS = 0 V, 10 V, VD = 10 V, 0 V VEN = 0 V VD = 0 V, 10 V VS = 10 V, 0 V V VEN = 0 V VS = VD = 0 V, 10 V VEN = 2.4 V VAL = 0.8 V VAH = 2.4 V DG428 DG429 DG428 DG429 Full Room Room Room Full Room Full Room Full Room Full Room Full 80 5 "0.03 "0.07 "0.05 "0.07 "0.05 -0.5 -50 -1 -100 -1 -50 -1 -100 -1 -50 0.5 50 1 100 1 50 1 100 1 50 -0.5 -50 -1 -100 -1 -50 -1 -100 -1 -50 0.5 50 1 100 1 50 1 100 1 50 nA A 0 12 150 0 12 150 V W %
A Suffix
-55 to 125_C
D Suffix
-40 to 85_C
Symbol
V+ = 12 V, V- = 0 V, WR = 0 RS = 2.4 V, VIN = 2.4 V, 0.8 Vf
Tempb
Typc
Mind
Maxd
Mind
Maxd
Unit
ID(off)
Drain On Leakage Current
ID(on)
Digital Control
Logic Input Current g p Input Voltage High I t V lt Hi h Logic Input Current Input Voltage Low IAH IAL VA = 2.4 V VA = 12 V VEN = 0 V, 2.4 V, VA = 0 V RS = 0 V, WR = 0 V Full Full Full -1 1 1 -1 1 1 mA A
Dynamic Characteristics
Transition Time Break-Before-Make Interval Enable and Write Turn-On Time Enable and Reset Turn-Off Time Charge Injection Off Isolation tTRANS tOPEN tON(EN, WR) tOFF(EN, RS) Q OIRR S1 = 10 V/2 V, S8 = 2 V/ 10 V See Figure 5 See Figure 4 S1 =5 V See Figures 6 and 7 S1 =5 V See Figures 6 and 8 VGEN = 6 V, RGEN = 0 W CL = 1 nF, See Figure 9 VEN = 0 V, RL = 300 W, CL = 15 pF VS = 7 VRMS, f = 100 kHz Room Full Room Full Room Full Room Full Room Room 160 40 110 70 4 -75 25 10 300 400 300 400 280 350 25 10 300 400 300 400 pC dB 280 350
ns
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Document Number: 70063 S-52433--Rev. J, 06-Sep-99
DG428/429
Vishay Siliconix
SPECIFICATIONSa FOR SINGLE SUPPLY
Test Conditions Unless Otherwise Specified Parameter Symbol
V+ = 12 V, V- = 0 V, WR = 0 RS = 2.4 V, VIN = 2.4 V, 0.8 Vf
A Suffix
-55 to 125_C
D Suffix
-40 to 85_C
Tempb
Typc
Mind
Maxd
Mind
Maxd
Unit
Minimum Input Timing Requirements
Write Pulse Width AX, EN Data Set Up Time AX, EN Data Hold Time Reset Pulse Width tW tS tH tRS VS = 5 V, See Figure 3 See Figure 2 S Fi Full Full Full Full 100 100 10 100 100 100 ns 10 100
Power Supplies
Positive Supply Current Notes: a. b. c. d. e. f. g. Refer to PROCESS OPTION FLOWCHART. Room = 25_C, Full = as determined by the operating temperature suffix. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. Guaranteed by design, not subject to production test. VIN = input voltage to perform proper function. r DS(on) MAX - r DS(on) MIN Dr DS(on) + x 100% r AVE
DS(on)
I+
VEN = 0 V, VA = 0, RS = 5 V
Room
20
100
100
mA
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TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
rDS(on) vs. VD and Supply Voltage
140 r DS(on) Drain-Source On-Resistance ( W ) - 120 100 80 60 40 20 0 -20 -16 -12 -8 "10 V "12 V "15 V "8 V "5 V r DS(on) Drain-Source On-Resistance ( W ) - 100 90 80 70 60 50 40 30 20 10 0 -4 0 4 8 12 16 20 -15 -10 -5 0 5 10 15 VD - Drain Voltage (V) -40_C V+ = 15 V V- = -15 V 25_C -55_C 125_C 85_C
rDS vs. VD and Temperature
"20 V
VD - Drain Voltage (V)
200 r DS(on) Drain-Source On-Resistance ( W ) -
Single Supply rDS(on) vs. VD and Supply
40 V- = 0 V 30
ID, IS Leakage Currents vs. Analog Voltage
V+ = 15 V V- = -15 V VS = -VD for ID(off) VD = VS for ID(on)
160
V+ = 7.5 V I S, I D - Current (pA) 20 10
120
10 V 12 V
IS(off) 0 -10 -20 ID(on), ID(off)
80
15 V 20 V
40
0 0 4 8 12 16 20
-30 -15 -10 -5 0 5 10 15 VD - Drain Voltage (V) VS,VD - Source, Drain Voltage (V)
ID, IS Leakages vs. Temperature
10 nA V+ = 15 V V- = -15 V VS, VD = "14 V I S, I D - Leakage Current 1 nA 250
Switching Times vs. Power Supply Voltage
200 tTRANS
100 pA
ID(on), ID(off)
Time (ns)
IS (off)
150
100
tON(EN)
10 pA 50
tOFF(EN)
1 pA -55 -35 -15 5 25 45 65 85 105 125
0 "5 "10 "15 "20 Temperature (C_) Supply Voltage (V)
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Document Number: 70063 S-52433--Rev. J, 06-Sep-99
DG428/429
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Switching Times vs. Single Supply
350 V- = 0 V 300 40 250 Q - Charge (pC) 20 0 -20 -40 -60 0 5 10 15 20 -15 -10 -5 0 5 10 15 V+ - Positive Supply (V) VS - Source Voltage (V) V+ = 15 V V- = -15 V Time (ms) 200 tTRANS 150 tON 100 tOFF 50 V+ = 12 V V- = 0 V 60
Charge Injection vs. Analog Voltage
Off-Isolation vs. Frequency
-140 8 6 -120 4 Supply Current (ma) -100 OIRR (dB) 2
Supply Current vs. Switching Frequency
EN = 5 V AX = 0 or 5 V I+
IGND 0 -2 -4 -6 I- -8
-80
-60
-40
-20 1k 10 k 100 k f - Frequency (Hz) 1M 10 M
1k
10 k
100 k f - Frequency (Hz)
1M
10 M
Switching Times vs. Temperature
200 V+ = 15 V V- = -15 V 150 2 Time (nS) tON V TH (V) tTRANS 3
Input Switching Threshold vs. PositiveSupply Voltage
2.5
100
1.5
tOFF 50
1
0.5
0 -55 -35
0 -15 5 25 45 65 85 105 125 0 5 10 15 20
Temperature (C_)
V+ Positive - Supply Voltage (V)
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DG428/429
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SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+ GND VREF D EN DO QO V+ V- AX Dn Qn Level Shift Decode/ Drive S1
Latches WR V+ RS V- V- CLK RESET
Sn
FIGURE 1.
TIMING DIAGRAMS
3V 3V WR 0V tW tS A0, A1, (A2) EN 3V 0V 20% 80% tH Switch Output 0V VO 80% 50% RS 0V tRS tOFF(RS) 50%
FIGURE 2.
FIGURE 3.
TEST CIRCUITS
+15 V V+ All S and Da +5 V tr <20 ns tf <20 ns 50% 0V
+2.4 V
RS EN
Logic Input
3V
DG428 DG429
A0, A1, (A2) GND 50 W WR Db, D V- 300 W 35 pF Switch Output VO 0V tOPEN VO VS 80%
-15 V
FIGURE 4. Break-Before-Make
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DG428/429
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TEST CIRCUITS
+15 V RS EN S2 - S7 A0 A1 A2 GND 50 W -15 V Switch Output +15 V +2.4 V RS EN A0 A1 GND 50 W -15 V V+ S1b S1a - S4a, Da S2b and S3b #10 V VO 0V 10% VS8 tTRANS S1 ON VO 35 pF tTRANS S8 ON tr <20 ns tf <20 ns 50% 0V 35 pF VS1 90% V+ S1 "10 V
+2.4 V
DG428
WR V-
S8 D 300 W
#10 V VO
Logic Input
3V
DG429
WR V-
S4b Db 300 W
#10 V
FIGURE 5. Transition Time
+15 V V+ RS EN A0 A1 A2 GND 50 W WR V- S1 -5V
+2.4 V
DG428
S2 - S8
D 300 W
VO 35 pF Logic Input
3V 50% 0V tON(EN) 0V
tr <20 ns tf <20 ns
-15 V
tOFF(EN)
+15 V V+ RS EN A0 A1 GND 50 W WR V- 300 W -15 V S1b -5V Switch Output VO VO 90%
+2.4 V
DG429
S1a - S4a, Da S2b - S4b Db VO 35 pF
FIGURE 6. Enable tON/tOFF Time
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DG428/429
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TEST CIRCUITS
+15 V V+
+2.4 V
EN A0, A1, (A2)
S1 or S1b Remaining Switches
+5 V WR
3V 50% 0V VO tON(WR) Switch Output 20% 0V
RS
DG428
Db, D V- 300 W -15 V 35 pF VO
DG429 WR GND
FIGURE 7. Write Turn-On Time tON(WR)
+15 V
+2.4 V
EN A0, A1, (A2)
V+
S1 or S1b Remaining Switches
+5 V
3V RS 0V tOFF(RS) VO VO 35 pF Switch Output 0V 80% 50%
RS GND
DG42 DG429
WR
Db, D V- 300 W -15 V
FIGURE 8. Reset Turn-Off Time tOFF(RS)
+15 V
V+ A0, A1, (A2) Rg S IN 3V GND WR
RS D
2.4 V VO CL 1 nF
OFF EN VO
ON
OFF DVO
Vg
V- DVO is the measured voltage error due to charge injection. The charge in coulombs is Q = CL x DVO
-15 V
FIGURE 9. Charge Injection
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DETAILED DESCRIPTION APPLICATIONS
The internal structure of the DG428/DG429 includes a 5-V logic interface with input protection circuitry followed by a latch, level shifter, decoder and finally the switch constructed with parallel n- and p-channel MOSFETs (see Figure 1).
Bus Interfacing The DG428/DG429 minimize the amount of interface hardware between a microprocessor system bus and the analog system being controlled or measured. The internal TTL compatible latches give these multiplexers write-only memory, that is, they can be programmed to stay in a particular switch state (e.g., switch 1 on) until the microprocessor determines it is necessary to turn different switches on or turn all switches off (see Figure 10). The input latches become transparent when WR is held low; therefore, these multiplexers operate by direct command of the coded switch state on A2, A1, A0. In this mode the DG428 is identical to the popular DG408. The same is true of the DG429 versus the popular DG409. During system power-up, RS would be low, maintaining all eight switches in the off state. After RS returned high the DG428 maintains all switches in the off state. When the system program performs a write operation to the address assigned to the DG428, the address decoder provides a CS active low signal which is gated with the WRITE (WR) control signal. At this time the data on the DATA BUS (that will determine which switch to close) is stabilizing. When the WR signal returns to the high state, (positive edge) the input latches of the DG428 save the data from the DATA BUS. The coded information in the A0, A1, A2 and EN latches is decoded and the appropriate switch is turned on. The EN latch allows all switches to be turned off under program control. This becomes useful when two or more DG428s are cascaded to build 16-line and larger multiplexers.
The input protection on the logic lines A0, A1, A2, EN and control lines WR, RS shown in Figure 1 minimizes susceptibility to ESD that may be encountered during handling and operational transients.
The logic interface is a CMOS logic input with its supply voltage from an internal +5 V reference voltage. The output of the input inverter feeds the data input of a D type latch. The level sensitive D latch continuously places the DX input signal on the QX output when the WR input is low, resulting in transparent latch operation. As soon as WR returns high the latch holds the data last present on the Dn input, subject to the "Minimum Input Timing Requirements" table.
Following the latches the Qn signals are level shifted and decoded to provide proper drive levels for the CMOS switches. This level shifting ensures full on/off switch operation for any analog signal level between the V+ and V- supply rails.
The EN pin is used to enable the address latches during the WR pulse. It can be hard wired to the logic supply or to V+ if one of the channels will always be used (except during a reset) or it can be tied to address decoding circuitry for memory mapped operation. The RS pin is used as a master reset. All latches are cleared regardless of the state of any other latch or control line. The WR pin is used to transfer the state of the address control lines to their latches, except during a reset or when EN is low (see Truth Tables).
+15 V S1
V+
"15 V Analog Inputs
Data Bus
A0, A1, A2, EN
DG428
Processor System Bus RESET +5 V S8 WRITE Address Bus Address Decoder - 15 V WR V- D Analog Output RS
FIGURE 10.Bus Interface
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